diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-29 22:39:04 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-07-09 11:37:44 +0200 |
| commit | 2568528f55356a2f20f80a18244d3e235cbd2cab (patch) | |
| tree | 4b91c4d1d83e00fe9b7289898d066dd12095e497 /drivers/clk/meson/meson8b.h | |
| parent | e653b41131f60054dbfa0c7431613d6aeaee2212 (diff) | |
clk: meson: meson8b: add the vclk2_en gate clock
HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However,
the GXBB driver defines this bit as a gate called "vclk2" and in the
3.10 kernel GPL code dump the following line can found:
WRITE_LCD_CBUS_REG_BITS(HHI_VIID_CLK_CNTL, 0, 19, 1); //disable vclk2_en
Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller to
complete the VCLK2 clock tree.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200629203904.2989007-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson/meson8b.h')
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index c8ab2a632295..699c5bc7c817 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -181,8 +181,9 @@ #define CLKID_CTS_MCLK_I958_SEL 210 #define CLKID_CTS_MCLK_I958_DIV 211 #define CLKID_VCLK_EN 214 +#define CLKID_VCLK2_EN 215 -#define CLK_NR_CLKS 215 +#define CLK_NR_CLKS 216 /* * include the CLKID and RESETID that have |