Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.4

Highlights
- new SoCs (G12B family): S922X, A311D
- new SoCs (SM1 family): S905X3
- new board: SEI Robotics SEI610 (SM1/S905X3)
- new board: Khadas VIM3 (G12B/A311D)
- DVFS/CPUfreq support on G12[AB] family

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits)
  arm64: dts: add support for SM1 based SEI Robotics SEI610
  dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings
  dt-bindings: arm: amlogic: add SM1 bindings
  arm64: dts: meson-g12b-odroid-n2: enable DVFS
  arm64: dts: meson-g12b-khadas-vim3: add initial device-tree
  dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml
  arm64: dts: amlogic: g12 CPU timers stop in suspend
  arm64: dts: meson-g12b: support a311d and s922x cpu operating points
  dt-bindings: arm: amlogic: add support for the Khadas VIM3
  dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC
  dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC
  arm64: dts: meson: add video decoder entries
  arm64: dts: meson-gx: add video decoder entry
  dt-bindings: media: amlogic,vdec: add default compatible
  arm64: dts: meson: add ethernet fifo sizes
  arm64: dts: meson-g12b: add cpus OPP tables
  arm64: dts: meson-g12a: enable DVFS on G12A boards
  arm64: dts: meson-g12a: add cpus OPP table
  arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux
  arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
  ...

Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 73 insertions, 0 deletions

diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c
new file mode 100644
index 000000000000..36976927fe82
--- /dev/null
+++ b/drivers/clk/meson/clk-cpu-dyndiv.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+
+#include "clk-regmap.h"
+#include "clk-cpu-dyndiv.h"
+
+static inline struct meson_clk_cpu_dyndiv_data *
+meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)
+{
+	return (struct meson_clk_cpu_dyndiv_data *)clk->data;
+}
+
+static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
+						      unsigned long prate)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
+
+	return divider_recalc_rate(hw, prate,
+				   meson_parm_read(clk->map, &data->div),
+				   NULL, 0, data->div.width);
+}
+
+static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
+					    unsigned long rate,
+					    unsigned long *prate)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
+
+	return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
+}
+
+static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
+					  unsigned long parent_rate)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
+	unsigned int val;
+	int ret;
+
+	ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
+	if (ret < 0)
+		return ret;
+
+	val = (unsigned int)ret << data->div.shift;
+
+	/* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */
+	meson_parm_write(clk->map, &data->dyn, 1);
+
+	/* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */
+	return regmap_update_bits(clk->map, data->div.reg_off,
+				  SETPMASK(data->div.width, data->div.shift) |
+				  SETPMASK(data->dyn.width, data->dyn.shift),
+				  val);
+};
+
+const struct clk_ops meson_clk_cpu_dyndiv_ops = {
+	.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
+	.round_rate = meson_clk_cpu_dyndiv_round_rate,
+	.set_rate = meson_clk_cpu_dyndiv_set_rate,
+};
+EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
+
+MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_LICENSE("GPL v2");