diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-30 12:41:48 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:20 +0200 |
| commit | 1561380ee72f55e3a86856ee046532c18d3e9855 (patch) | |
| tree | ab72974348d7530f90d9c7aa4adf23a81d5657a6 /drivers/clk/mediatek/clk-gate.c | |
| parent | 0ab55cf1834177a2162757fee2ac3cb6730beb20 (diff) | |
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.
This patch adds support for generating FOUTPOSTDIV clk.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/mediatek/clk-gate.c')
0 files changed, 0 insertions, 0 deletions