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| author | Jaewon Kim <jaewon02.kim@samsung.com> | 2024-03-28 18:10:00 +0900 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-03-31 12:19:12 +0200 |
| commit | 04ee3a0b44e3d18cf6b0c712d14b98624877fd26 (patch) | |
| tree | a031f7a86663ef4f0964b0953881b9ffd07e7703 /drivers/clk/Makefile | |
| parent | 98784a9d398ea5513cf571835be7e45885ba49ab (diff) | |
clk: samsung: exynosautov9: fix wrong pll clock id value
All PLL id values of CMU_TOP were incorrectly set to FOUT_SHARED0_PLL.
It modified to the correct PLL clock id value.
Fixes: 6587c62f69dc ("clk: samsung: add top clock support for Exynos Auto v9 SoC")
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240328091000.17660-1-jaewon02.kim@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/clk/Makefile')
0 files changed, 0 insertions, 0 deletions