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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-29 08:39:02 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-13 09:38:05 +0200 |
| commit | 1f89aa906fac1d569ecf8f427b1edca6e26fa472 (patch) | |
| tree | 6a86856dd0efa582e68ffcd4427aaa82bfaabfc7 /drivers/cdx/controller/cdx_controller.c | |
| parent | 77e18969da3a5a0ed5f7c3b80869c0acf25377ab (diff) | |
pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets
SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S.
Add a per SoC configuration data structure that is initialized with the
proper register offsets for individual SoCs. The rzg2l_hwcfg structure
will be extended further in later commits.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-16-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/cdx/controller/cdx_controller.c')
0 files changed, 0 insertions, 0 deletions