diff options
| author | Joshua Yeong <joshua.yeong@starfivetech.com> | 2024-05-15 13:02:52 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2024-05-28 12:34:11 +0100 |
| commit | cabff60ca77da6cb460988e2af40bde95776d92b (patch) | |
| tree | b997127aa411bd3bb023f43a1ca235317a7b7275 /drivers/cache/Kconfig | |
| parent | c6005d4dd216a5eb0837432511cc87c9a19c5c9e (diff) | |
cache: Add StarFive StarLink cache management
Add StarFive Starlink cache management driver.
The driver enables RISC-V non-standard cache
operation on SoC that does not support Zicbom
extension instructions.
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers/cache/Kconfig')
| -rw-r--r-- | drivers/cache/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 9345ce4976d7..94abd8f632a7 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -14,4 +14,13 @@ config SIFIVE_CCACHE help Support for the composable cache controller on SiFive platforms. +config STARFIVE_STARLINK_CACHE + bool "StarFive StarLink Cache controller" + depends on RISCV + depends on ARCH_STARFIVE + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + help + Support for the StarLink cache controller IP from StarFive. + endmenu |