diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2022-09-08 08:42:27 -0700 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-09-17 16:34:54 +0800 |
| commit | 21e24d257fe23ff53f6db3b4af2f06c07766396e (patch) | |
| tree | 32b1a89d80d5ef400b89fda6b66ec4f4da5c91e1 /arch | |
| parent | a90a37bbeab4518cc3bf5c4d1eb088cf8993fcf9 (diff) | |
arm64: dts: imx8mp-venice-gw74xx: add USB DR support
Add support for USB DR on USB1 interface. Host/Device detection is done
using the usb-role-switch connector with a GPIO as USB1_OTG_ID is not
connected internally.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index 521215520a0f..d3f7cc66bab8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -563,20 +563,35 @@ }; /* USB1 - Type C front panel */ -&usb3_phy0 { +&usb3_0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; status = "okay"; }; -&usb3_0 { - fsl,over-current-active-low; +&usb3_phy0 { status = "okay"; }; &usb_dwc3_0 { - dr_mode = "host"; + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; status = "okay"; + + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; }; /* USB2 - USB3.0 Hub */ @@ -825,7 +840,12 @@ pinctrl_usb1: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 - MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usbcon1: usb1congrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; |