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authorJonathan Corbet <corbet@lwn.net>2019-06-14 14:18:53 -0600
committerJonathan Corbet <corbet@lwn.net>2019-06-14 14:18:53 -0600
commit8afecfb0ec961e37e61b2d19c4fa71617a9482de (patch)
treec43ea51a47b1e76b762caa4c1b0c356249e5e874 /arch/x86/platform/intel-mid/pwr.c
parentce1a5ea18ef9bf4c62c75abe7c540a29264ec988 (diff)
parentd1fdb6d8f6a4109a4263176c84b899076a5f8008 (diff)
Merge tag 'v5.2-rc4' into mauro
We need to pick up post-rc1 changes to various document files so they don't get lost in Mauro's massive RST conversion push.
Diffstat (limited to 'arch/x86/platform/intel-mid/pwr.c')
-rw-r--r--arch/x86/platform/intel-mid/pwr.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 49ec5b94c71f..27288d8d3f71 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel MID Power Management Unit (PWRMU) device driver
*
@@ -5,10 +6,6 @@
*
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
* Intel MID Power Management Unit device driver handles the South Complex PCI
* devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
* modifies bits in PMCSR register in the PCI configuration space. This is not