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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-06-13 23:49:23 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-06-13 23:49:23 +0200 |
| commit | ae892d150fe6da09ce00cf469ea6f326a9435ee2 (patch) | |
| tree | d3e8823b97000c0df1e5310e74cfbf8ee96c5cf1 /arch/x86/kernel/cpu/intel.c | |
| parent | d352cf47d93e39494b44b792cca8d35a3a0bd9b3 (diff) | |
| parent | b77b5651082a4fa4091ac4e864254d9e71d15880 (diff) | |
Merge branch 'x86/cpu'
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 6e2ffbebbcdb..c1a89bc026ac 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c) } /* - * P4 Xeon errata 037 workaround. + * P4 Xeon erratum 037 workaround. * Hardware prefetcher may cause stale data to be loaded into the cache. */ if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { if (msr_set_bit(MSR_IA32_MISC_ENABLE, - MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) - > 0) { + MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { pr_info("CPU: C0 stepping P4 Xeon detected.\n"); - pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); + pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); } } |