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| author | Takashi Iwai <tiwai@suse.de> | 2022-12-22 09:11:48 +0100 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2022-12-22 09:11:48 +0100 |
| commit | 2d78eb0342dd2c9c5cde9ae9ada1d33f189a858b (patch) | |
| tree | f711bc9cab45f4963e4883ef15ff4c54a6cbc12e /arch/x86/include/asm/spec-ctrl.h | |
| parent | b47068b4aa53a57552398e3f60d0ed1918700c2b (diff) | |
| parent | ee0b089d660021792e4ab4dda191b097ce1e964f (diff) | |
Merge branch 'for-next' into for-linus
Diffstat (limited to 'arch/x86/include/asm/spec-ctrl.h')
| -rw-r--r-- | arch/x86/include/asm/spec-ctrl.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h index 5393babc0598..cb0386fc4dc3 100644 --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -13,7 +13,7 @@ * Takes the guest view of SPEC_CTRL MSR as a parameter and also * the guest's version of VIRT_SPEC_CTRL, if emulated. */ -extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest); +extern void x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool guest); /** * x86_spec_ctrl_set_guest - Set speculation control registers for the guest @@ -24,9 +24,9 @@ extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bo * Avoids writing to the MSR if the content/bits are the same */ static inline -void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) +void x86_spec_ctrl_set_guest(u64 guest_virt_spec_ctrl) { - x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true); + x86_virt_spec_ctrl(guest_virt_spec_ctrl, true); } /** @@ -38,9 +38,9 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) * Avoids writing to the MSR if the content/bits are the same */ static inline -void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) +void x86_spec_ctrl_restore_host(u64 guest_virt_spec_ctrl) { - x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false); + x86_virt_spec_ctrl(guest_virt_spec_ctrl, false); } /* AMD specific Speculative Store Bypass MSR data */ |