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| author | Ingo Molnar <mingo@kernel.org> | 2024-01-26 10:26:50 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2024-01-26 10:26:50 +0100 |
| commit | 42ac0be18bfa09c03f52244f7c3e15c89b38532f (patch) | |
| tree | 601fd5e6da2ca0b77aa8cb22f0e81a29ba6fe1d6 /arch/x86/include/asm/processor.h | |
| parent | 8e5647a723c49d73b9f108a8bb38e8c29d3948ea (diff) | |
| parent | ecb1b8288dc7ccbdcb3b9df005fa1c0e0c0388a7 (diff) | |
Merge branch 'linus' into x86/mm, to refresh the branch and pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/include/asm/processor.h')
| -rw-r--r-- | arch/x86/include/asm/processor.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index ae81a7191c1c..26620d7642a9 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -749,4 +749,22 @@ enum mds_mitigations { extern bool gds_ucode_mitigated(void); +/* + * Make previous memory operations globally visible before + * a WRMSR. + * + * MFENCE makes writes visible, but only affects load/store + * instructions. WRMSR is unfortunately not a load/store + * instruction and is unaffected by MFENCE. The LFENCE ensures + * that the WRMSR is not reordered. + * + * Most WRMSRs are full serializing instructions themselves and + * do not require this barrier. This is only required for the + * IA32_TSC_DEADLINE and X2APIC MSRs. + */ +static inline void weak_wrmsr_fence(void) +{ + alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); +} + #endif /* _ASM_X86_PROCESSOR_H */ |