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| author | Dmitry Torokhov <[email protected]> | 2020-01-10 14:56:04 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <[email protected]> | 2020-01-10 14:56:04 -0800 |
| commit | 1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c (patch) | |
| tree | 2244894a9ea0c941a8f32e5f3d196b4ea0eae24b /arch/x86/include/asm/cpufeatures.h | |
| parent | 643dd7416649bea2e8c61d8fdeeefb409a0ca5eb (diff) | |
| parent | c79f46a282390e0f5b306007bf7b11a46d529538 (diff) | |
Merge tag 'v5.5-rc5' into next
Sync up with mainline to get SPI "delay" API changes.
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 0652d3eed9bd..e9b62498fe75 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -292,6 +292,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ @@ -399,5 +400,7 @@ #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ +#define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ +#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ #endif /* _ASM_X86_CPUFEATURES_H */ |