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authorLendacky, Thomas <Thomas.Lendacky@amd.com>2014-07-02 13:04:34 -0500
committerDavid S. Miller <davem@davemloft.net>2014-07-07 21:38:06 -0700
commit91f873453b70fe6cdb83409bee68e1023204c381 (patch)
tree044848d5cb059abc032487e472a953a2c8d5fbbf /arch/sparc
parentf3f128d40c4cc263af8e30b009a3eb17655e912b (diff)
amd-xgbe: Clear the proper MTL interrupt register
When initializing the MTL interrupts the interrupt status register is written to instead of the interrupt enable register. Since no MTL interrupts are being enabled and the default state is for MTL interrupts to be disabled this did not cause a problem, but needs to be fixed to target the correct register. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc')
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