diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-16 19:24:00 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-16 19:24:00 -0700 |
commit | 8d2b6b3ae280dcf6f6c7a95623670a57cdf562ed (patch) | |
tree | 79e0c663f37c380735a41031abaa73b4c299c9ca /arch/sh/include/uapi/asm/auxvec.h | |
parent | 90a24a4a7e8f8b3488438276e1d15bb3762df31e (diff) | |
parent | 0dd4d5cbe4c38165dc9b3ad329ebb23f24d74fdb (diff) |
Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
Pull SuperH updates from Paul Mundt.
The bulk of this is the UAPI disintegration for SH.
* tag 'sh-for-linus' of git://github.com/pmundt/linux-sh:
sh: Fix up more fallout from pointless ARM __iomem churn.
sh: Wire up kcmp syscall.
UAPI: (Scripted) Disintegrate arch/sh/include/asm
Diffstat (limited to 'arch/sh/include/uapi/asm/auxvec.h')
-rw-r--r-- | arch/sh/include/uapi/asm/auxvec.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/sh/include/uapi/asm/auxvec.h b/arch/sh/include/uapi/asm/auxvec.h new file mode 100644 index 000000000000..8bcc51af9367 --- /dev/null +++ b/arch/sh/include/uapi/asm/auxvec.h @@ -0,0 +1,38 @@ +#ifndef __ASM_SH_AUXVEC_H +#define __ASM_SH_AUXVEC_H + +/* + * Architecture-neutral AT_ values in 0-17, leave some room + * for more of them. + */ + +/* + * This entry gives some information about the FPU initialization + * performed by the kernel. + */ +#define AT_FPUCW 18 /* Used FPU control word. */ + +#if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__) +/* + * Only define this in the vsyscall case, the entry point to + * the vsyscall page gets placed here. The kernel will attempt + * to build a gate VMA we don't care about otherwise.. + */ +#define AT_SYSINFO_EHDR 33 +#endif + +/* + * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + * value is -1, then the cache doesn't exist. Otherwise: + * + * bit 0-3: Cache set-associativity; 0 means fully associative. + * bit 4-7: Log2 of cacheline size. + * bit 8-31: Size of the entire cache >> 8. + */ +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 + +#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ + +#endif /* __ASM_SH_AUXVEC_H */ |