diff options
| author | Chris Morgan <[email protected]> | 2023-10-18 11:18:46 -0500 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2023-11-16 21:25:55 +0100 |
| commit | 48794cd57a67246acc53a3edfdececdbb5b98453 (patch) | |
| tree | 86c8f53953759effe4e1c7f08d3210e08367580c /arch/s390/lib/test_modules_helpers.c | |
| parent | b85ea95d086471afb4ad062012a4d73cd328fa86 (diff) | |
clk: rockchip: rk3568: Add PLL rate for 115.2MHz
Add support for a PLL rate of 115.2MHz so that the Powkiddy RK2023 panel
can run at a requested 60hz (59.99, close enough).
I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."
Signed-off-by: Chris Morgan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'arch/s390/lib/test_modules_helpers.c')
0 files changed, 0 insertions, 0 deletions