diff options
| author | Samuel Holland <samuel@sholland.org> | 2023-02-11 20:15:33 -0600 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-02-14 16:10:36 -0800 |
| commit | d5a7fab7859dc88657372a448b78babcf134114e (patch) | |
| tree | 1cc3864525de02f3439db5267a67ed36f904039f /arch/riscv/lib/strcmp.S | |
| parent | bfd6fc5d80145e12d0ffa144c4bad89b8f9ddc5a (diff) | |
riscv: Fix Zbb alternative IDs
Commit 4bf8860760d9 ("riscv: cpufeature: extend
riscv_cpufeature_patch_func to all ISA extensions") switched ISA
extension alternatives to use the RISCV_ISA_EXT_* macros instead of
CPUFEATURE_*. This was mismerged when applied on top of the Zbb series,
so the Zbb alternatives referenced the wrong errata ID values.
Fixes: 9daca9a5b9ac ("Merge patch series "riscv: improve boot time isa extensions handling"")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230212021534.59121-3-samuel@sholland.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/lib/strcmp.S')
| -rw-r--r-- | arch/riscv/lib/strcmp.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/lib/strcmp.S b/arch/riscv/lib/strcmp.S index 8148b6418f61..986ab23fe787 100644 --- a/arch/riscv/lib/strcmp.S +++ b/arch/riscv/lib/strcmp.S @@ -9,7 +9,7 @@ /* int strcmp(const char *cs, const char *ct) */ SYM_FUNC_START(strcmp) - ALTERNATIVE("nop", "j strcmp_zbb", 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB) + ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB) /* * Returns |