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authorAndrew Jones <[email protected]>2023-12-13 18:09:56 +0100
committerAnup Patel <[email protected]>2023-12-29 12:31:47 +0530
commit6ccf119a4cc886678099a3526f37db98b67024d7 (patch)
tree3775c08b15df38cc0a51bfd8e8d6718487b238d4 /arch/riscv/kvm/vcpu_vector.c
parent23e1dc45022eb65529aa30b1851a8d21a639c8f5 (diff)
KVM: riscv: selftests: Add RISCV_SBI_EXT_REG
While adding RISCV_SBI_EXT_REG(), acknowledge that some registers have subtypes and extend __kvm_reg_id() to take a subtype field. Then, update all macros to set the new field appropriately. The general CSR macro gets renamed to include "GENERAL", but the other macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype. Signed-off-by: Andrew Jones <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'arch/riscv/kvm/vcpu_vector.c')
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