diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-01-02 22:27:08 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-01-26 16:02:16 +0100 |
| commit | 7dd48e96d0cda9af79a2fee85e9135b4781f9ee1 (patch) | |
| tree | 240fb2f6461056c8ca615f20034d92b3911cb331 /arch/riscv/include | |
| parent | 87d85b48f8109980c83b57b37ba963949ffbef25 (diff) | |
riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}
IRQC support for RZ/Five is still missing so drop the interrupts and
interrupt-parent properties from the PHY nodes of ETH{0,1}.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102222708.274369-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/riscv/include')
0 files changed, 0 insertions, 0 deletions