aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv/errata/andes
diff options
context:
space:
mode:
authorAndrew Jones <ajones@ventanamicro.com>2023-12-13 18:09:55 +0100
committerAnup Patel <anup@brainfault.org>2023-12-29 12:31:44 +0530
commit23e1dc45022eb65529aa30b1851a8d21a639c8f5 (patch)
tree8818e02c12a9afff71dae224803a9f37ce88ea62 /arch/riscv/errata/andes
parent7602730d7f18ad9738d8fc5e5fd7f52a11fee399 (diff)
RISC-V: KVM: Make SBI uapi consistent with ISA uapi
When an SBI extension cannot be enabled, that's a distinct state vs. enabled and disabled. Modify enum kvm_riscv_sbi_ext_status to accommodate it, which allows KVM userspace to tell the difference in state too, as the SBI extension register will disappear when it cannot be enabled, i.e. accesses to it return ENOENT. get-reg-list is updated as well to only add SBI extension registers to the list which may be enabled. Returning ENOENT for SBI extension registers which cannot be enabled makes them consistent with ISA extension registers. Any SBI extensions which were enabled by default are still enabled by default, if they can be enabled at all. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/errata/andes')
0 files changed, 0 insertions, 0 deletions