omap4: l2x0: Set share override bit

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption

Signed-off-by: Santosh Shilimkar <[email protected]>
Tested-by: Nishanth Menon <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>

0 files changed, 0 insertions, 0 deletions