diff options
| author | Archit Taneja <architt@codeaurora.org> | 2015-07-29 12:14:12 -0400 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2017-02-06 11:28:45 -0500 |
| commit | 34d9545b9f769c6553e31a6820c9cb51f5e93099 (patch) | |
| tree | 7f6bfe43053230360044c2a69119713a3f058fa8 /arch/mips/xilfpga/init.c | |
| parent | 57bf433893370c069a0c34842f35a3bb8aa130fc (diff) | |
drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
In case of dual DSI, some registers in PHY1 have been programmed
during PLL0 clock's set_rate. The PHY1 reset called by host1 later
will silently reset those PHY1 registers. This change is to reset
and enable both PHYs before any PLL clock operation.
[Originally worked on by Hai Li <hali@codeaurora.org>. Fixed up
by Archit Taneja <architt@codeaurora.org>]
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'arch/mips/xilfpga/init.c')
0 files changed, 0 insertions, 0 deletions