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| author | Dinh Nguyen <dinguyen@kernel.org> | 2017-01-25 10:01:28 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2017-01-25 10:01:28 -0600 |
| commit | 59d94d2ed45d598211feb52566e6a806d17f8a3f (patch) | |
| tree | a64401c658f7a67a57a2554d9e18fc0f19581812 /arch/mips/netlogic/common/smp.c | |
| parent | 7f0f5460d46867a8f980683136a054cff1357780 (diff) | |
ARM: dts: watchdog0 cannot reliably trigger reset
On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger
a reset to the CPU. The workaround would be to use watchdog1 instead.
Also for watchdog1, there is a dependency on the bootloader to enable the
boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This
corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the
control register in the clock manager module of Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/mips/netlogic/common/smp.c')
0 files changed, 0 insertions, 0 deletions