diff options
| author | Dmitry Torokhov <[email protected]> | 2020-01-10 14:56:04 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <[email protected]> | 2020-01-10 14:56:04 -0800 |
| commit | 1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c (patch) | |
| tree | 2244894a9ea0c941a8f32e5f3d196b4ea0eae24b /arch/mips/kernel/traps.c | |
| parent | 643dd7416649bea2e8c61d8fdeeefb409a0ca5eb (diff) | |
| parent | c79f46a282390e0f5b306007bf7b11a46d529538 (diff) | |
Merge tag 'v5.5-rc5' into next
Sync up with mainline to get SPI "delay" API changes.
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 342e41de9d64..83f2a437d9e2 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1761,7 +1761,7 @@ static inline void parity_protection_init(void) case CPU_5KC: case CPU_5KE: - case CPU_LOONGSON1: + case CPU_LOONGSON32: write_c0_ecc(0x80000000); back_to_back_c0_hazard(); /* Set the PE bit (bit 31) in the c0_errctl register. */ @@ -2394,7 +2394,7 @@ void __init trap_init(void) else { if (cpu_has_vtag_icache) set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); - else if (current_cpu_type() == CPU_LOONGSON3) + else if (current_cpu_type() == CPU_LOONGSON64) set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); else set_except_vector(EXCCODE_RI, handle_ri_rdhwr); |