diff options
| author | Weijie Gao <hackpascal@gmail.com> | 2016-03-17 06:34:09 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-04-03 12:32:09 +0200 |
| commit | c338d59d12dc93c3287160acd7e726b56dc94f43 (patch) | |
| tree | f26c90d90253ebd00fac0d964b152f09a9bc2fba /arch/mips/kernel/module-rela.c | |
| parent | 2b885ea66f4cb15cc3812dc90ddfb3b6b0567561 (diff) | |
MIPS: ath79: Fix the ar724x clock calculation
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.
The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.
This patch is compatible with the current calculation procedure with
default FB and REF_DIV values.
Tested on AR7240, AR7241 and AR7242.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Alban Bedel <albeu@free.fr> (Fixed the commit log message)
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12870/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/module-rela.c')
0 files changed, 0 insertions, 0 deletions