diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 15:42:10 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 15:42:10 +0100 |
| commit | 7a5c3b8c5c27211846efe7029a3d2ee7087425e3 (patch) | |
| tree | 92530366912b64c2826a882a79ebcfbe6ec28d59 /arch/mips/include/asm/mach-db1x00/db1200.h | |
| parent | 39b741431af7f6f46b2e0e7f7f13ea2351fb4a5f (diff) | |
| parent | 2af99920d56debcf879ac71a1934e8fcccdc713e (diff) | |
Merge branch 'next/alchemy' into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm/mach-db1x00/db1200.h')
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/db1200.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 7a39657108c4..b2a8319521e5 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -43,15 +43,20 @@ #define BCSR_INT_PC1EJECT 0x0800 #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 +#define BCSR_INT_SD1INSERT 0x4000 +#define BCSR_INT_SD1EJECT 0x8000 -#define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR +#define DB1200_IDE_PHYS_ADDR 0x18800000 #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) #define DB1200_ETH_PHYS_ADDR 0x19000300 #define DB1200_NAND_PHYS_ADDR 0x20000000 +#define PB1200_IDE_PHYS_ADDR 0x0C800000 +#define PB1200_ETH_PHYS_ADDR 0x0D000300 +#define PB1200_NAND_PHYS_ADDR 0x1C000000 + /* * External Interrupts for DBAu1200 as of 8/6/2004. * Bit positions in the CPLD registers can be calculated by taking @@ -77,6 +82,8 @@ enum external_db1200_ints { DB1200_PC1_EJECT_INT, DB1200_SD0_INSERT_INT, DB1200_SD0_EJECT_INT, + PB1200_SD1_INSERT_INT, + PB1200_SD1_EJECT_INT, DB1200_INT_END = DB1200_INT_BEGIN + 15, }; |