aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
diff options
context:
space:
mode:
authorMaxime Bizon <mbizon@freebox.fr>2013-06-04 22:53:35 +0100
committerDavid S. Miller <davem@davemloft.net>2013-06-10 14:28:28 -0700
commit6f00a0229627ca189529cad3f9154ac2f9e5c7db (patch)
tree20b010b5faa5fca26951f3f3575da92a9cf317fc /arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
parent0ae99b5fede6f3a8d252d50bb4aba29544295219 (diff)
bcm63xx_enet: add support for Broadcom BCM63xx integrated gigabit switch
Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch which needs to be driven slightly differently from the traditional external switches. This patch introduces changes in arch/mips/bcm63xx in order to: - register a bcm63xx_enetsw driver instead of bcm63xx_enet driver - update DMA channels configuration & state RAM base addresses - add a new platform data configuration knob to define the number of ports per switch/device and force link on some ports - define the required switch registers On the driver side, the following changes are required: - the switch ports need to be polled to ensure the link is up and running and RX/TX can properly work - basic switch configuration needs to be performed for the switch to forward packets to the CPU - update the MIB counters since the integrated Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index d53f611184b9..118e3c938841 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -39,7 +39,35 @@ struct bcm63xx_enet_platform_data {
int phy_id, int reg, int val));
};
+/*
+ * on board ethernet switch platform data
+ */
+#define ENETSW_MAX_PORT 8
+#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
+
+#define ENETSW_RGMII_PORT0 4
+
+struct bcm63xx_enetsw_port {
+ int used;
+ int phy_id;
+
+ int bypass_link;
+ int force_speed;
+ int force_duplex_full;
+
+ const char *name;
+};
+
+struct bcm63xx_enetsw_platform_data {
+ char mac_addr[ETH_ALEN];
+ int num_ports;
+ struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
+};
+
int __init bcm63xx_enet_register(int unit,
const struct bcm63xx_enet_platform_data *pd);
+int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
+
#endif /* ! BCM63XX_DEV_ENET_H_ */