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authorNeil Armstrong <neil.armstrong@linaro.org>2023-06-12 17:22:52 +0200
committerBjorn Andersson <andersson@kernel.org>2023-06-13 11:01:49 -0700
commitbb47bfbd5aa89368c348d9828484f7201cef6cea (patch)
treea8b2fe3a0586fcfa4363f423039d53ae69a9f92f /arch/arm64
parenta791fc19965e52918bb70e2b764965083eaadbed (diff)
arm64: dts: qcom: sm8550-qrd: enable PMIC Volume and Power buttons
The Volume Down & Power buttons are controlled by the PMIC via the PON hardware, and the Volume Up is connected to a PMIC gpio. Enable the necessary hardware and setup the GPIO state for the Volume Up gpio key. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-4-a288f24af81b@linaro.org
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/qcom/sm8550-qrd.dts36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index efff15225e67..cde2ab8b18a4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -54,6 +54,22 @@
stdout-path = "serial0:115200n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
pmic-glink {
compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
@@ -516,6 +532,16 @@
};
};
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
&pm8550_pwm {
status = "okay";
@@ -548,6 +574,16 @@
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
&pcie_1_phy_aux_clk {
clock-frequency = <1000>;
};