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authorJason Gunthorpe <jgg@mellanox.com>2018-12-11 14:24:57 -0700
committerJason Gunthorpe <jgg@mellanox.com>2018-12-11 14:24:57 -0700
commit28ab1bb0e8f031dd7dd3462ff8f6b2e93fc77e7f (patch)
tree3c0d2177d9bfc513c2d06c1efb5ab62c74fd1953 /arch/arm64/kernel/cpufeature.c
parentb874155a5fa450bf5e4b5303cbfff05958805bf8 (diff)
parent40e020c129cfc991e8ab4736d2665351ffd1468d (diff)
Merge tag 'v4.20-rc6' into rdma.git for-next
For dependencies in following patches.
Diffstat (limited to 'arch/arm64/kernel/cpufeature.c')
-rw-r--r--arch/arm64/kernel/cpufeature.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index af50064dea51..aec5ecb85737 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1333,7 +1333,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.cpu_enable = cpu_enable_hw_dbm,
},
#endif
-#ifdef CONFIG_ARM64_SSBD
{
.desc = "CRC32 instructions",
.capability = ARM64_HAS_CRC32,
@@ -1343,6 +1342,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
.min_field_value = 1,
},
+#ifdef CONFIG_ARM64_SSBD
{
.desc = "Speculative Store Bypassing Safe (SSBS)",
.capability = ARM64_SSBS,