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| author | Ralf Baechle <ralf@linux-mips.org> | 2016-08-03 12:55:49 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-08-03 12:55:49 +0200 |
| commit | 4a89cf810130fde41e3fc729e770cb1a5a87d245 (patch) | |
| tree | 84da40f8d26e51c21e61fc4fc5b7242c0050ae7d /arch/arm64/kernel/cpu_errata.c | |
| parent | 4f53989b0652ffe2605221c81ca8ffcfc90aed2a (diff) | |
| parent | e9cbf6299e306d6f2ff7b8fe7ac66059191b182f (diff) | |
Merge branch '4.7-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/arm64/kernel/cpu_errata.c')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d42789499f17..af716b65110d 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -98,6 +98,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, (1 << MIDR_VARIANT_SHIFT) | 1), }, + { + /* Cavium ThunderX, T81 pass 1.0 */ + .desc = "Cavium erratum 27456", + .capability = ARM64_WORKAROUND_CAVIUM_27456, + MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), + }, #endif { } |