diff options
| author | Mark Brown <broonie@kernel.org> | 2022-07-04 18:02:46 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-07-05 11:45:46 +0100 |
| commit | f13d54697bbeff19c13774f7af1fd267d696f0e4 (patch) | |
| tree | 5669ef84e048d03937c58054ac5288583ec9cf8c /arch/arm64/include | |
| parent | 9a2f3290bb101146246eaf3f807bdc9718b56e49 (diff) | |
arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums
We have a series of defines for enumeration values we test for in the
fields in ID_AA64SMFR0_EL1 which do not follow our usual convention of
including the EL1 in the name and having _IMP at the end of the basic
"feature present" define. In preparation for automatic register
generation bring the defines into sync with convention, no functional
change.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-13-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/el2_setup.h | 2 | ||||
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 30 |
2 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 34ceff08cac4..bfd0ad64b598 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -161,7 +161,7 @@ mov x1, #0 // SMCR controls mrs_s x2, SYS_ID_AA64SMFR0_EL1 - ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM? + ubfx x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM? cbz x2, .Lskip_sme_fa64_\@ orr x1, x1, SMCR_ELx_FA64_MASK diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1b1ea5bd01c0..3c77cf850f36 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -834,21 +834,21 @@ #define ID_AA64ZFR0_SVEVER_SVE2 0x1 /* id_aa64smfr0 */ -#define ID_AA64SMFR0_FA64_SHIFT 63 -#define ID_AA64SMFR0_I16I64_SHIFT 52 -#define ID_AA64SMFR0_F64F64_SHIFT 48 -#define ID_AA64SMFR0_I8I32_SHIFT 36 -#define ID_AA64SMFR0_F16F32_SHIFT 35 -#define ID_AA64SMFR0_B16F32_SHIFT 34 -#define ID_AA64SMFR0_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_FA64 0x1 -#define ID_AA64SMFR0_I16I64 0xf -#define ID_AA64SMFR0_F64F64 0x1 -#define ID_AA64SMFR0_I8I32 0xf -#define ID_AA64SMFR0_F16F32 0x1 -#define ID_AA64SMFR0_B16F32 0x1 -#define ID_AA64SMFR0_F32F32 0x1 +#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 +#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 +#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 +#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 +#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 +#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 +#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 + +#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 +#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf +#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 +#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf +#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 +#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 +#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 |