diff options
| author | Mark Brown <broonie@kernel.org> | 2022-07-04 18:02:55 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-07-05 11:45:47 +0100 |
| commit | 8fcc8285c0e312a6d5ec6060c67eba87d2881419 (patch) | |
| tree | 9ea59008a1102f47399a76ad9c185314d2d2bbc1 /arch/arm64/include | |
| parent | f7b5115cc39cfbe49a1d0b57605c918237e1b8c2 (diff) | |
arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions
in DDI0487H.a. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7f87690e74b3..cd6820f6e819 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,8 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) - #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) @@ -699,31 +697,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar2 */ -#define ID_AA64ISAR2_EL1_BC_SHIFT 28 -#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 -#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 -#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 -#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 - -/* - * Value 0x1 has been removed from the architecture, and is - * reserved, but has not yet been removed from the ARM ARM - * as of ARM DDI 0487G.b. - */ -#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 -#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_EL1_APA3_NI 0x0 -#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 -#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 -#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 -#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 -#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 - /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 |