diff options
| author | Vignesh Raghavendra <vigneshr@ti.com> | 2023-03-20 10:19:34 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-03-20 12:34:25 -0500 |
| commit | 6974371cab1c488a53960945cb139b20ebb5f16b (patch) | |
| tree | dd45411797f90c3f9f9674b25ef9095f1b4e17a4 /arch/arm64/boot/dts/ti/k3-am625.dtsi | |
| parent | 436b288687176bf4d2c1cd25b86173e5a1649a60 (diff) | |
arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB
Per AM62x SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am625 Page 1.
Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am625.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index acc7f8ab6426..4193c2b3eed6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -148,7 +148,7 @@ compatible = "cache"; cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; |