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authorMarijn Suijten <marijn.suijten@somainline.org>2023-07-23 18:08:41 +0200
committerBjorn Andersson <andersson@kernel.org>2023-09-19 14:38:03 -0700
commit3d06cee2249f4764f01a9f602ec1cc1bf4562ca6 (patch)
treeb114b92e5e0bf1e877003f2b7ed84f7c001b8d66 /arch/arm64/boot/dts/qcom/sm6125.dtsi
parent310cdafc4a56827d1aeda7cc297939034adb8f99 (diff)
arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg
This node has always resided in the wrong spot, making it somewhat harder to contribute new node entries while maintaining proper sorting around it. Move the node up to sit after hsusb_phy1 where it maintains proper numerical sorting on the (first of its many) reg address property. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-3-a3f287dd6c07@somainline.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6125.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm6125.dtsi36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 197f8fed19a2..9e5cac45fa75 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -683,6 +683,24 @@
status = "disabled";
};
+ spmi_bus: spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x01c40000 0x1100>,
+ <0x01e00000 0x2000000>,
+ <0x03e00000 0x100000>,
+ <0x03f00000 0xa0000>,
+ <0x01c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x045f0000 0x7000>;
@@ -1188,24 +1206,6 @@
reg = <0x04690000 0x10000>;
};
- spmi_bus: spmi@1c40000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x01c40000 0x1100>,
- <0x01e00000 0x2000000>,
- <0x03e00000 0x100000>,
- <0x03f00000 0xa0000>,
- <0x01c0a000 0x26000>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0c600000 0x80000>;