diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-11-07 09:04:16 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-12-07 08:14:01 -0800 |
| commit | b0e0290bc47dd1bc8b1bd0c6b9ec0347564f3f21 (patch) | |
| tree | 82c89d0b702dbab16901b78040eeb4a1c29a7107 /arch/arm64/boot/dts/qcom/qdu1000.dtsi | |
| parent | 11fcb81373de52eeb1d3ff135a8d24a4b18978d3 (diff) | |
arm64: dts: qcom: qdu1000: correct LLCC reg entries
According to bindings and Linux driver there is no
"multi_channel_register" address space for LLCC. The first "reg" entry
is supposed to be llcc0_base since commit 43aa006e074c ("dt-bindings:
arm: msm: Fix register regions used for LLCC banks"):
qdu1000-idp.dtb: system-cache-controller@19200000: reg: [[0, 421527552, 0, 14155776], [0, 438304768, 0, 524288], [0, 572293416, 0, 4]] is too long
qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:0: 'llcc0_base' was expected
qdu1000-idp.dtb: system-cache-controller@19200000: reg-names: ['llcc_base', 'llcc_broadcast_base', 'multi_channel_register'] is too long
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20231107080417.16700-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/qdu1000.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qdu1000.dtsi | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 1c0e5d271e91..618a101eb53a 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1446,11 +1446,9 @@ system-cache-controller@19200000 { compatible = "qcom,qdu1000-llcc"; reg = <0 0x19200000 0 0xd80000>, - <0 0x1a200000 0 0x80000>, - <0 0x221c8128 0 0x4>; - reg-names = "llcc_base", - "llcc_broadcast_base", - "multi_channel_register"; + <0 0x1a200000 0 0x80000>; + reg-names = "llcc0_base", + "llcc_broadcast_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; multi-ch-bit-off = <24 2>; }; |