diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2019-08-09 18:33:21 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-08-14 15:36:22 +0200 |
| commit | a1f487d75c9be17421f1ab10172427dd16e5f56a (patch) | |
| tree | cbe8f8cd2927564f2e97e8a91f2b166e2c08b5b0 /arch/arm/mach-iop32x/irqs.h | |
| parent | ba9ef6afc45ff4eb2d9c6e26c6a94279ee3b4348 (diff) | |
ARM: iop32x: merge everything into mach-iop32x/
Various bits of iop32x are now in their traditional locations in plat-iop,
mach-iop/include/mach/ and in include/asm/mach/hardware. As nothing
outside of the iop32x mach code references these any more, this can all
be moved into one place now.
The only remaining things in the include/mach/ directory are now the
NR_IRQS definition, the entry-macros.S file and the the decompressor
uart access. After the irqchip code has been converted to SPARSE_IRQ
and GENERIC_IRQ_MULTI_HANDLER, it can be moved to ARCH_MULTIPLATFORM.
Link: https://lore.kernel.org/r/20190809163334.489360-7-arnd@arndb.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-iop32x/irqs.h')
| -rw-r--r-- | arch/arm/mach-iop32x/irqs.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h new file mode 100644 index 000000000000..69858e4e905d --- /dev/null +++ b/arch/arm/mach-iop32x/irqs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Rory Bolt <rorybolt@pacbell.net> + * Copyright: (C) 2002 Rory Bolt + */ + +#ifndef __IOP32X_IRQS_H +#define __IOP32X_IRQS_H + +/* + * IOP80321 chipset interrupts + */ +#define IRQ_IOP32X_DMA0_EOT 0 +#define IRQ_IOP32X_DMA0_EOC 1 +#define IRQ_IOP32X_DMA1_EOT 2 +#define IRQ_IOP32X_DMA1_EOC 3 +#define IRQ_IOP32X_AA_EOT 6 +#define IRQ_IOP32X_AA_EOC 7 +#define IRQ_IOP32X_CORE_PMON 8 +#define IRQ_IOP32X_TIMER0 9 +#define IRQ_IOP32X_TIMER1 10 +#define IRQ_IOP32X_I2C_0 11 +#define IRQ_IOP32X_I2C_1 12 +#define IRQ_IOP32X_MESSAGING 13 +#define IRQ_IOP32X_ATU_BIST 14 +#define IRQ_IOP32X_PERFMON 15 +#define IRQ_IOP32X_CORE_PMU 16 +#define IRQ_IOP32X_BIU_ERR 17 +#define IRQ_IOP32X_ATU_ERR 18 +#define IRQ_IOP32X_MCU_ERR 19 +#define IRQ_IOP32X_DMA0_ERR 20 +#define IRQ_IOP32X_DMA1_ERR 21 +#define IRQ_IOP32X_AA_ERR 23 +#define IRQ_IOP32X_MSG_ERR 24 +#define IRQ_IOP32X_SSP 25 +#define IRQ_IOP32X_XINT0 27 +#define IRQ_IOP32X_XINT1 28 +#define IRQ_IOP32X_XINT2 29 +#define IRQ_IOP32X_XINT3 30 +#define IRQ_IOP32X_HPI 31 + +#endif |