diff options
| author | Rodrigo Vivi <[email protected]> | 2018-07-23 09:13:12 -0700 | 
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2018-07-23 09:13:12 -0700 | 
| commit | c74a7469f97c0f40b46e82ee979f9fb1bb6e847c (patch) | |
| tree | f2690a1a916b73ef94657fbf0e0141ae57701825 /arch/arm/mach-exynos/platsmp.c | |
| parent | 6f15a7de86c8cf2dc09fc9e6d07047efa40ef809 (diff) | |
| parent | 500775074f88d9cf5416bed2ca19592812d62c41 (diff) | |
Merge drm/drm-next into drm-intel-next-queued
We need a backmerge to get DP_DPCD_REV_14 before we push other
i915 changes to dinq that could break compilation.
Signed-off-by: Rodrigo Vivi <[email protected]>
Diffstat (limited to 'arch/arm/mach-exynos/platsmp.c')
| -rw-r--r-- | arch/arm/mach-exynos/platsmp.c | 27 | 
1 files changed, 21 insertions, 6 deletions
| diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 5156fe70e030..6a1e682371b3 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -163,6 +163,26 @@ int exynos_cluster_power_state(int cluster)  		S5P_CORE_LOCAL_PWR_EN);  } +/** + * exynos_scu_enable : enables SCU for Cortex-A9 based system + */ +void exynos_scu_enable(void) +{ +	struct device_node *np; +	static void __iomem *scu_base; + +	if (!scu_base) { +		np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); +		if (np) { +			scu_base = of_iomap(np, 0); +			of_node_put(np); +		} else { +			scu_base = ioremap(scu_a9_get_base(), SZ_4K); +		} +	} +	scu_enable(scu_base); +} +  static void __iomem *cpu_boot_reg_base(void)  {  	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) @@ -219,11 +239,6 @@ static void write_pen_release(int val)  	sync_cache_w(&pen_release);  } -static void __iomem *scu_base_addr(void) -{ -	return (void __iomem *)(S5P_VA_SCU); -} -  static DEFINE_SPINLOCK(boot_lock);  static void exynos_secondary_init(unsigned int cpu) @@ -389,7 +404,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)  	exynos_set_delayed_reset_assertion(true);  	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) -		scu_enable(scu_base_addr()); +		exynos_scu_enable();  	/*  	 * Write the address of secondary startup into the |