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authorTudor Ambarus <tudor.ambarus@linaro.org>2023-03-28 10:15:15 +0000
committerNicolas Ferre <nicolas.ferre@microchip.com>2023-03-30 21:20:59 +0200
commit09ce8651229bb2d8e10ce0499e07da6f9bfaf5d8 (patch)
treede60881f199d9af6ea652cd2b0fe3f6f0324ba86 /arch/arm/boot/dts/stih418-b2199.dts
parent417e58ea41abe4c7f8be22ab5034b5e11f952240 (diff)
ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency
sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230328101517.1595738-3-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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