diff options
| author | Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> | 2023-06-20 16:31:37 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-07-19 13:09:54 -0700 |
| commit | 64446fe08c55dfa1f4489bc6366545c7180268b8 (patch) | |
| tree | 482f39cae56aedf887c88a86522fdbe297e3ea8b /Documentation | |
| parent | bbb8eb3cb06f66866726ddacfbf7c1411a40565d (diff) | |
dt-bindings: clock: versal: Add versal-net compatible string
Add dt-binding documentation for Versal NET platforms.
Versal Net is a new AMD/Xilinx SoC.
The SoC and its architecture is based on the Versal ACAP device.
The Versal Net device includes more security features in the
platform management controller (PMC) and increases the number of
CPUs in the application processing unit (APU) and the real-time
processing unit (RPU).
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20230620110137.5701-1-shubhrajyoti.datta@amd.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 5cbb34d0b61b..e9cf747bf89b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -18,7 +18,12 @@ select: false properties: compatible: - const: xlnx,versal-clk + oneOf: + - const: xlnx,versal-clk + - items: + - enum: + - xlnx,versal-net-clk + - const: xlnx,versal-clk "#clock-cells": const: 1 |