diff options
author | Dipen Patel <dipenp@nvidia.com> | 2023-04-13 17:44:49 -0700 |
---|---|---|
committer | Dipen Patel <dipenp@nvidia.com> | 2023-04-26 15:43:02 -0700 |
commit | 1815e37b6e67f2a543e36628bfe6a834aad3ea1b (patch) | |
tree | c8e9b6e9e002096dd623c2ef43009ca6637c3e2e /Documentation | |
parent | d0672fa4931dcb9d9d53002e855f25dd7507a300 (diff) |
dt-bindings: timestamp: Deprecate nvidia,slices property
The property is not necessary as it is a constant value and can be
hardcoded in the driver code.
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index 5de1eca9cbcd..456797967adc 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -42,10 +42,13 @@ properties: nvidia,slices: $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and the value depends on the HTE instance in the chip. + property and the value depends on the HTE instance in the chip. The AON + GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 + LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] nvidia,gpio-controller: @@ -66,7 +69,6 @@ required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" allOf: @@ -123,7 +125,6 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; #timestamp-cells = <1>; }; @@ -133,7 +134,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; }; |