diff options
| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2024-06-20 03:36:25 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-08-05 21:43:15 +0530 |
| commit | c4b09c562086f32588d962d30d0b7e93fe3e7cbb (patch) | |
| tree | defd3d921751947f27fe1ab7b38bdf67db94230c /Documentation/netlink | |
| parent | a652f2210054276990d45626a3b9ad5c99465f5a (diff) | |
phy: phy-rockchip-samsung-hdptx: Add clock provider support
The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC
CRU. It provides more accurate clock rates required by VOP2 to improve
existing support for display modes handling, which is known to be
problematic when dealing with non-integer refresh rates, among others.
It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be
used to support HDMI 2.1 4K@120Hz mode.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-4-6a2d2164e508@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'Documentation/netlink')
0 files changed, 0 insertions, 0 deletions