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| author | Ed Swierk <[email protected]> | 2017-07-19 17:47:31 -0700 |
|---|---|---|
| committer | Zhang Rui <[email protected]> | 2017-08-08 16:59:08 +0800 |
| commit | 23c973f59057929118ff3c80834d7d0335842c63 (patch) | |
| tree | 81289539a3517589f74b4395b069436a21ad1436 /Documentation/filesystems/caching/backend-api.txt | |
| parent | a742fc10bd7faafa2023c941e4e2c8c20f28aa8a (diff) | |
thermal: intel_pch_thermal: Read large temp values correctly
On all supported platforms, the TS Reading (TSR) field in the
Temperature (TEMP) register is 9 bits wide. Values above 0x100 (78
degrees C) are plausible, so don't mask out the topmost bit. And the
register itself is 16 bits wide, so use readw() rather than readl().
Signed-off-by: Ed Swierk <[email protected]>
Reviewed-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Zhang Rui <[email protected]>
Diffstat (limited to 'Documentation/filesystems/caching/backend-api.txt')
0 files changed, 0 insertions, 0 deletions