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| author | Andy Shevchenko <[email protected]> | 2020-11-10 21:59:23 +0200 |
|---|---|---|
| committer | Andy Shevchenko <[email protected]> | 2020-11-12 15:54:45 +0200 |
| commit | bf8b7e689de22f862c4b066ff73d8267e04905e2 (patch) | |
| tree | 08406e2a30b071a823fc9478d0747ff91afdb6c0 /Documentation/filesystems/caching/backend-api.rst | |
| parent | 1d112baae84844f3737193c39ac5069f5980ecd1 (diff) | |
pinctrl: jasperlake: Unhide SPI group of pins
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Mika Westerberg <[email protected]>
Diffstat (limited to 'Documentation/filesystems/caching/backend-api.rst')
0 files changed, 0 insertions, 0 deletions