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| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-06-20 13:10:39 +0200 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-08-07 14:32:10 -0700 |
| commit | 5e46ad83db102ce36ec4d47a62e115b7ac812311 (patch) | |
| tree | 5b98b4ae0184da743fdaa82c8b131aaae37a5612 /Documentation/filesystems/caching/backend-api.rst | |
| parent | 29af7605453797b9b58c3369314bd5710f5ea2ba (diff) | |
drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start
While it's not very well understood, there is some sort of a fault
handler implemented in the GMU firmware which triggers when a certain
bit is set, resulting in the M3 core not booting up the way we expect
it to.
Write a magic value to a magic register to hopefully prevent that
from happening.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543335/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'Documentation/filesystems/caching/backend-api.rst')
0 files changed, 0 insertions, 0 deletions