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| author | Yong Wu <[email protected]> | 2021-01-11 19:18:52 +0800 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2021-02-01 11:31:17 +0000 |
| commit | 00ab6f2d61583e072a0cced0420ee1134d853a35 (patch) | |
| tree | 7cd5d0ba1649f00175dc9c73466a294c393c35b7 /Documentation/filesystems/caching/backend-api.rst | |
| parent | 40596d2f2b6075f6c33180b2f55c814ff4885475 (diff) | |
iommu/io-pgtable-arm-v7s: Clarify LVL_SHIFT/BITS macro
The current _ARM_V7S_LVL_BITS/ARM_V7S_LVL_SHIFT use a formula to calculate
the corresponding value for level1 and level2 to pretend the code sane.
Actually their level1 and level2 values are different from each other.
This patch only clarify the two macro. No functional change.
Suggested-by: Robin Murphy <[email protected]>
Signed-off-by: Yong Wu <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'Documentation/filesystems/caching/backend-api.rst')
0 files changed, 0 insertions, 0 deletions