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| author | Roger Quadros <[email protected]> | 2020-01-06 15:06:22 +0200 |
|---|---|---|
| committer | Kishon Vijay Abraham I <[email protected]> | 2020-01-14 10:50:19 +0530 |
| commit | c9f9eba06629cd813c21df3327a1013ad092e988 (patch) | |
| tree | e9764936cb6a28002bfda36cebefd5ef18a66619 /Documentation/driver-api/fpga/fpga-programming.rst | |
| parent | 6385cbe9c567cb85ba40b6af09ad2f506e71158d (diff) | |
phy: ti: j721e-wiz: Manage typec-gpio-dir
Based on this GPIO state we need to configure LN10
bit to swap lane0 and lane1 if required (flipped connector).
Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.
Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).
Use the DT property to figure out if we need to add delay
or not before sampling the Type-C DIR line.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Reviewed-by: Jyri Sarha <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Diffstat (limited to 'Documentation/driver-api/fpga/fpga-programming.rst')
0 files changed, 0 insertions, 0 deletions