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| author | Thierry Reding <[email protected]> | 2021-07-08 16:37:36 +0200 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2021-12-16 14:07:07 +0100 |
| commit | 271fca025a6d43f1c18a48543c5aaf31a31e4694 (patch) | |
| tree | 0a6c900d75eefbf41ff57d181e9dbf311ef6a995 /Documentation/driver-api/fpga/fpga-programming.rst | |
| parent | 6c7a388b62366f0de9936db3c1921d7f4e0011bc (diff) | |
drm/tegra: gr2d: Explicitly control module reset
As of commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks"), module resets are no longer automatically deasserted when the
module clock is enabled. To make sure that the gr2d module continues to
work, we need to explicitly control the module reset.
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'Documentation/driver-api/fpga/fpga-programming.rst')
0 files changed, 0 insertions, 0 deletions