diff options
author | Mike Marshall <hubcap@omnibond.com> | 2016-03-14 15:39:42 -0400 |
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committer | Mike Marshall <hubcap@omnibond.com> | 2016-03-14 15:39:42 -0400 |
commit | ab6652524aaf834d5dcdb46dd7695813b8d63da5 (patch) | |
tree | bb3876a9b61254be902416f7dbf578deb28e9f22 /Documentation/devicetree/bindings/usb/dwc3-xilinx.txt | |
parent | acfcbaf1925f2dc5c46c61de69d756dec92a2ff8 (diff) | |
parent | b562e44f507e863c6792946e4e1b1449fbbac85d (diff) |
Orangefs: merge to v4.5
Merge tag 'v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into current
Linux 4.5
Diffstat (limited to 'Documentation/devicetree/bindings/usb/dwc3-xilinx.txt')
-rw-r--r-- | Documentation/devicetree/bindings/usb/dwc3-xilinx.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt new file mode 100644 index 000000000000..30361b32a460 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt @@ -0,0 +1,33 @@ +Xilinx SuperSpeed DWC3 USB SoC controller + +Required properties: +- compatible: Should contain "xlnx,zynqmp-dwc3" +- clocks: A list of phandles for the clocks listed in clock-names +- clock-names: Should contain the following: + "bus_clk" Master/Core clock, have to be >= 125 MHz for SS + operation and >= 60MHz for HS operation + + "ref_clk" Clock source to core during PHY power down + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Example device node: + + usb@0 { + #address-cells = <0x2>; + #size-cells = <0x1>; + status = "okay"; + compatible = "xlnx,zynqmp-dwc3"; + clock-names = "bus_clk" "ref_clk"; + clocks = <&clk125>, <&clk125>; + ranges; + + dwc3@fe200000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe200000 0x40000>; + interrupts = <0x0 0x41 0x4>; + dr_mode = "host"; + }; + }; |