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author | Jason Gunthorpe <jgg@mellanox.com> | 2018-12-11 14:24:57 -0700 |
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committer | Jason Gunthorpe <jgg@mellanox.com> | 2018-12-11 14:24:57 -0700 |
commit | 28ab1bb0e8f031dd7dd3462ff8f6b2e93fc77e7f (patch) | |
tree | 3c0d2177d9bfc513c2d06c1efb5ab62c74fd1953 /Documentation/devicetree/bindings/spi | |
parent | b874155a5fa450bf5e4b5303cbfff05958805bf8 (diff) | |
parent | 40e020c129cfc991e8ab4736d2665351ffd1468d (diff) |
Merge tag 'v4.20-rc6' into rdma.git for-next
For dependencies in following patches.
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r-- | Documentation/devicetree/bindings/spi/spi-uniphier.txt | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt index 504a4ecfc7b1..b04e66a52de5 100644 --- a/Documentation/devicetree/bindings/spi/spi-uniphier.txt +++ b/Documentation/devicetree/bindings/spi/spi-uniphier.txt @@ -5,18 +5,20 @@ UniPhier SoCs have SCSSI which supports SPI single channel. Required properties: - compatible: should be "socionext,uniphier-scssi" - reg: address and length of the spi master registers - - #address-cells: must be <1>, see spi-bus.txt - - #size-cells: must be <0>, see spi-bus.txt - - clocks: A phandle to the clock for the device. - - resets: A phandle to the reset control for the device. + - interrupts: a single interrupt specifier + - pinctrl-names: should be "default" + - pinctrl-0: pin control state for the default mode + - clocks: a phandle to the clock for the device + - resets: a phandle to the reset control for the device Example: spi0: spi@54006000 { compatible = "socionext,uniphier-scssi"; reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; resets = <&peri_rst 11>; }; |