Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "Device-tree updates for arm64 platforms. For the first time I can
  remember, this is actually larger than the corresponding branch for
  32-bit platforms overall, though that has more individual changes.

  A significant portion this time is due to added machine support:

   - Initial support for the Realtek RTD1295 SoC, along with the Zidoo
     X9S set-top-box

   - Initial support for Actions Semi S900 and the Bubblegum-96
     single-board-cёmputer.

   - Rockchips support for the rk3399-Firefly single-board-computer gets
     added, this one stands out for being relatively fast, affordable
     and well₋supported, compared to many boards that only fall into one
     or two of the above categories.

   - Mediatek gains support for the mt6797 mobile-phone SoC platform and
     corresponding evaluation board.

   - Amlogic board support gets added for the NanoPi K2 and S905x
     LibreTech CC single-board computers and the R-Box Pro set-top-box

   - Allwinner board support gets added for the OrangePi Win, Orangepi
     Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers
     and the SoPine system-on-module.

   - Renesas board support for Salvator-XS and H3ULCB automotive
     development systems.

   - Socionext Uniphier board support for LD11-global and LD20-global,
     whatever those may be.

   - Broadcom adds support for the new Stingray communication processor
     in its iProc family, along with two reference boards.

  Other updates include:

   - For the hisicon platform, support for Hi3660-Hikey960 gets extended
     significantly.

   - Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
     Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits)
  ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
  Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"
  arm64: dts: mediatek: don't include missing file
  ARM64: dts: meson-gxl: Add Libre Technology CC support
  dt-bindings: arm: amlogic: Add Libre Technology CC board
  dt-bindings: add Libre Technology vendor prefix
  arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
  arm64: dts: zte: Use - instead of @ for DT OPP entries
  arm64: dts: marvell: add gpio support for Armada 7K/8K
  arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  arm64: dts: marvell: use new binding for the system controller on cp110
  arm64: dts: marvell: remove *-clock-output-names on cp110
  arm64: dts: marvell: use new bindings for xor clocks on ap806
  arm64: dts: marvell: mcbin: enable the mdio node
  arm64: dts: Add Actions Semi S900 and Bubblegum-96
  dt-bindings: Add vendor prefix for uCRobotics
  arm64: dts: marvell: add xmdio nodes for 7k/8k
  arm64: dts: marvell: add a comment on the cp110 slave node status
  arm64: dts: marvell: remove cpm crypto nodes from dts files
  arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
  ...

1 files changed, 76 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index 6f66e9aa354c..f2c5f0e4a363 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -219,3 +219,79 @@ BCM63138
 --------
 PLL and leaf clock compatible strings for BCM63138 are:
     "brcm,bcm63138-armpll"
+
+Stingray
+-----------
+PLL and leaf clock compatible strings for Stingray are:
+    "brcm,sr-genpll0"
+    "brcm,sr-genpll1"
+    "brcm,sr-genpll2"
+    "brcm,sr-genpll3"
+    "brcm,sr-genpll4"
+    "brcm,sr-genpll5"
+    "brcm,sr-genpll6"
+
+    "brcm,sr-lcpll0"
+    "brcm,sr-lcpll1"
+    "brcm,sr-lcpll-pcie"
+
+
+The following table defines the set of PLL/clock index and ID for Stingray.
+These clock IDs are defined in:
+    "include/dt-bindings/clock/bcm-sr.h"
+
+    Clock		Source		Index	ID
+    ---			-----		-----	---------
+    crystal		N/A		N/A	N/A
+    crmu_ref25m		crystal		N/A	N/A
+
+    genpll0		crystal		0	BCM_SR_GENPLL0
+    clk_125m		genpll0		1	BCM_SR_GENPLL0_125M_CLK
+    clk_scr		genpll0		2	BCM_SR_GENPLL0_SCR_CLK
+    clk_250		genpll0		3	BCM_SR_GENPLL0_250M_CLK
+    clk_pcie_axi	genpll0		4	BCM_SR_GENPLL0_PCIE_AXI_CLK
+    clk_paxc_axi_x2	genpll0		5	BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
+    clk_paxc_axi	genpll0		6	BCM_SR_GENPLL0_PAXC_AXI_CLK
+
+    genpll1		crystal		0	BCM_SR_GENPLL1
+    clk_pcie_tl		genpll1		1	BCM_SR_GENPLL1_PCIE_TL_CLK
+    clk_mhb_apb		genpll1		2	BCM_SR_GENPLL1_MHB_APB_CLK
+
+    genpll2		crystal		0	BCM_SR_GENPLL2
+    clk_nic		genpll2		1	BCM_SR_GENPLL2_NIC_CLK
+    clk_ts_500_ref	genpll2		2	BCM_SR_GENPLL2_TS_500_REF_CLK
+    clk_125_nitro	genpll2		3	BCM_SR_GENPLL2_125_NITRO_CLK
+    clk_chimp		genpll2		4	BCM_SR_GENPLL2_CHIMP_CLK
+    clk_nic_flash	genpll2		5	BCM_SR_GENPLL2_NIC_FLASH
+
+    genpll3		crystal		0	BCM_SR_GENPLL3
+    clk_hsls		genpll3		1	BCM_SR_GENPLL3_HSLS_CLK
+    clk_sdio		genpll3		2	BCM_SR_GENPLL3_SDIO_CLK
+
+    genpll4		crystal		0	BCM_SR_GENPLL4
+    ccn			genpll4		1	BCM_SR_GENPLL4_CCN_CLK
+    clk_tpiu_pll	genpll4		2	BCM_SR_GENPLL4_TPIU_PLL_CLK
+    noc_clk		genpll4		3	BCM_SR_GENPLL4_NOC_CLK
+    clk_chclk_fs4	genpll4		4	BCM_SR_GENPLL4_CHCLK_FS4_CLK
+    clk_bridge_fscpu	genpll4		5	BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
+
+
+    genpll5		crystal		0	BCM_SR_GENPLL5
+    fs4_hf_clk		genpll5		1	BCM_SR_GENPLL5_FS4_HF_CLK
+    crypto_ae_clk	genpll5		2	BCM_SR_GENPLL5_CRYPTO_AE_CLK
+    raid_ae_clk		genpll5		3	BCM_SR_GENPLL5_RAID_AE_CLK
+
+    genpll6		crystal		0	BCM_SR_GENPLL6
+    48_usb		genpll6		1	BCM_SR_GENPLL6_48_USB_CLK
+
+    lcpll0		crystal		0	BCM_SR_LCPLL0
+    clk_sata_refp 	lcpll0		1	BCM_SR_LCPLL0_SATA_REFP_CLK
+    clk_sata_refn	lcpll0		2	BCM_SR_LCPLL0_SATA_REFN_CLK
+    clk_usb_ref		lcpll0		3	BCM_SR_LCPLL0_USB_REF_CLK
+    sata_refpn		lcpll0		3	BCM_SR_LCPLL0_SATA_REFPN_CLK
+
+    lcpll1		crystal		0	BCM_SR_LCPLL1
+    wan 		lcpll1		1	BCM_SR_LCPLL0_WAN_CLK
+
+    lcpll_pcie		crystal		0	BCM_SR_LCPLL_PCIE
+    pcie_phy_ref 	lcpll1		1	BCM_SR_LCPLL_PCIE_PHY_REF_CLK