diff options
| author | Clément Léger <cleger@rivosinc.com> | 2023-11-14 09:12:49 -0500 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-12-12 15:45:10 -0800 |
| commit | 74ba42b250a7339c72e5803490b1ea42c3556f26 (patch) | |
| tree | 74c722b0d5960140c3bdbac3693f4c295d504592 /Documentation/arch/riscv | |
| parent | eddbfa0d849fa5a315840e8c501962252b48484d (diff) | |
riscv: hwprobe: export Zhintntl ISA extension
Export Zihintntl extension[1] through hwprobe.
Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-14-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/arch/riscv')
| -rw-r--r-- | Documentation/arch/riscv/hwprobe.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 397d53195f49..aa8ebeeddfe6 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -146,6 +146,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. |